module RegExMem (
    input   [1:0]       Branch,
    input   [1:0]       MemToReg,
    input               MemWrite,
    input               RegWrite,
    input   [1:0]       Jump,
    input   [1:0]       DataType_in,
    input               DataSign_in,
    input   [31:0]      pc, 
    input   [31:0]      npc,
    input   [31:0]      alu_result,
    input               alu_zero,
    input   [31:0]      data_rt,
    input   [4:0]       des_reg,
    input               MemRead_in,
    input               clk,

    output reg   [1:0]     Branch_out,
    output reg   [1:0]     MemToReg_out,
    output reg             MemWrite_out,
    output reg             RegWrite_out,
    output reg   [1:0]     Jump_out,
    output reg   [1:0]     DataType_out,
    output reg             DataSign_out,
    output reg   [31:0]    pc_out,
    output reg   [31:0]    npc_out,
    output reg             alu_zero_out,
    output reg   [31:0]    alu_result_out,

    output reg   [31:0]    data_rt_out,
    output reg   [4:0]     des_reg_out,
    output reg             MemRead_out
    
  

);
    
    always @(posedge clk) begin
        MemRead_out = MemRead_in;
        Branch_out<=Branch;
        MemToReg_out<=MemToReg;
        MemWrite_out<= MemWrite;
        RegWrite_out<=RegWrite;
        Jump_out<=Jump;
        DataType_out <= DataType_in;
        DataSign_out <= DataSign_in;
        pc_out<= pc;
        npc_out<=npc;
        alu_result_out<=alu_result;
        alu_zero_out<=alu_zero;
        data_rt_out<=data_rt;
        des_reg_out<=des_reg;
    end
endmodule //reg_ex_mem